 | Understanding of basic digital concepts
 | Attributes
 | Ability to distinguish between digital and analog signals and data |
| Ability to compare and contrast digital and analog solutions to a
problem |
| Understanding of clocks and timing diagrams |
|
| SPU Goals: Competence |
| Engineering Goals: Competent in core disciplines |
|
| Understanding of basic combinational digital logic
| Attributes
| Ability to design combinational logic circuits |
| Ability to analyze, transform, and minimize combinational logic circuits |
| Ability to apply combinational logic circuits to real-world problems |
|
| SPU Goals: Competence |
| Engineering Goals: Competent in core disciplines |
|
| Understanding of advanced combinational digital logic
| Attributes
| Ability to design circuits using advanced combinational logic blocks |
| Understanding of multiplexors, decoders, encoders, and other advanced
combinational logic blocks |
|
| SPU Goals: Competence |
| Engineering Goals: Competent in core disciplines |
|
| Understanding of basic mathematical circuits
| Attributes:
| Understanding of binary mathematical functions |
| Ability to convert between binary, decimal, and hexadecimal
represenations |
| Ability to manipulate two's complement negative numbers |
| Ability to design and analyze simple adders and multipliers using
combinational logic |
|
| SPU Goals: Competence |
| Engineering Goals: |
|
| Understanding of basic sequential digital logic
| Attributes:
| Ability to design circuits using latches and flipflops |
| Ability to analyze the timing of sequential circuits |
| Understanding of how to construct latches and flipflops out of simple
combinational logic elements |
|
| SPU Goals: Competence |
| Engineering Goals: Competent in core disciplines |
|
| Understanding of counters and finite state machines
| Attributes:
| Ability to analyze an existing counter/fsm |
| Ability to design a counter/fsm to solve a real-world problem |
| Ability to build a counter/fsm out of basic combinational and sequential
logic building blocks |
|
| SPU Goals: Competence |
| Engineering Goals: Competent in core disciplines |
|
| Ability to build combinational logic circuits out of standard TTL/CMOS
parts
| Attributes: |
| SPU Goals: Competence |
| Engineering Goals: Prepared for a variety of post-graduate experiences,
Competent in core disciplines |
|
| Ability to use modern CAD tools for logic design
| Attributes:
| Familiarity with modern CPLDs and FPGAs |
| Ability to use CAD tools to design combinational and sequential
circuits in a CPLD |
| Ability to use CAD tools to analyze combinational and sequential
circuits in a CPLD |
| Ability to use VHDL to design medium-size circuits in a CPLD |
|
| SPU Goals: Competence |
| Engineering Goals: Prepared for a variety of post-graduate experiences,
Competent in core disciplines |
|
